sy89850u precision low - power lvpecl line driver/receiver with internal termination precision edge is a registered trademark of micrel, inc. august 2 007 m9999 -0 83007 -b hbwhelp@micrel.com or (408) 955 - 1690 general description the sy89850u is a 2.5v/3.3v precision, high - speed, differential receiver capable of handling clocks up to 4ghz and data streams up to 3.2gbps. the differential input includes micrel's unique, 3 - pin input termination architecture that allows users to interface to any differential signal (ac or dc - coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor networks in the signal path. the outputs are 800mv lvpecl, with extremely fast rise/fall times guaranteed to be less than 160ps. the sy89850u operates from a 2.5v 5% supply or a 3.3v 10% supply and is guaranteed over the full industrial temperature range of ? 40c to +85c. the sy89850u is part of micrel's high - speed, precision edge ? product line. all supp ort documentation can be found on micrel's web site at www.micrel.com . typical application precision edge ? features ? guaranteed ac performance over temperature and supply voltage: ? dc- to > 3.2gbps data rate throughput ? 4ghz clock f max (typ.) ? <280ps in - to - out t pd ? <160ps t r /t f ? low power: 50mw (2.5v typ.) ? ultra - low jitter design: ? <1ps rms random jitter ? <10ps pp deterministic jitter ? <10ps pp total jitter (clock) ? unique input termination and vt pin a ccepts dc - and ac - coupled inputs (cml, pecl, lvds) ? typical 800mv (100k) lvpecl output swing ? power supply 2.5v 5% or 3.3v 10% ? industrial temperature range ? 40c to +85c ? available in ultra - small (2mm x 2mm) 8 - pin dfn package applications ? backplane buffe ring ? oc - 12 to oc - 192 sonet/sdn clock/data distribution ? all gigabit ethernet clock or data distribution ? fibre channel distribution markets ? lan/wan ? enterprise s ervers ? ate ? test and m easurement
micrel, inc. sy89850u august 2 007 2 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 ordering information (1) part number package type operating range package marking lead finish sy89850umg dfn -8 industrial 850u with pb - free bar - line indicator nipdau pb - free sy89850umgtr (2) dfn -8 industrial 850u with pb - free bar - line indicator nipdau pb - free notes: 1. contact factory for dice availability. dice are guar anteed at t a = 25c, dc electrical only. 2. tape and reel. pin configuration 8 - pin dfn pin description pin number pin name pin function 1, 4 in, /in differential input: this input pair is the signal to be buffered. these inputs accept ac - or dc - coupled signals as small as 100mv. each pin of this pair internally terminates to a vt pin through 50 ?. note tha t this input will default to an indeterminate state if left open. please refer to the ?input interface applications? section for more details. 2 vt in put termination center - tap: each side of the differential input pair terminates to this pin. the vt pin provides a center - tap to a termination network for maximum interface flexibility. see ?input interface applications? section for more details. 3 vref -ac reference output voltage: this output biases to v cc ? 1.2v. connect to vt pin when ac - coupling the input. bypass with 0.01 p f low esr capacitor to v cc . maximum sink/source current is 1.5ma. due to the limited drive capability, the vref - ac pin is only intended to drive its respective vt pin. see ?input interface applications? section. 5 gnd, exposed pad ground: ground pin an d exposed pad must be connected to the same ground plane. 7, 6 q, /q differential 100k lvpecl output: this lvpecl output is the output of the device. terminate through 50 ? to v cc ? 2v. see ?output interface applications? section. 8 vcc positive power su pply: bypass with 0.1 p f//0.01 p f low esr capacitors as close to the vcc pin as possible.
micrel, inc. sy89850u august 2 007 3 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 absolute maximum ratings (1) supply voltage (v cc ) .......................... ? 0.5v to +4.0v input voltage (v in ) .................................. ? 0.5v to v cc lvpecl output current (i out ) ................................... continuous .................................................. 50ma surge ........................................................ 100ma input c urrent .............................................................. source or sink current on in, /in .............. 50ma termination current ................................................... source or sink current on vt .................. 100ma source or sink current on v ref?ac ..................... 2ma lead temperature (soldering, 20sec.) ............. 260c storage temperature (t s ) ............... ? 65c to +150c operating ratings (2) supp ly voltage (v cc ) .................. +2.375v to +2.625v ...................................................... +3.0v to +3.6v ambient temperature (t a ) ................ ? 40c to +85c package thermal resistance (3) dfn ( ja ) still - air ..................................................... 93c/w dfn ( jb ) junction - to - board .................................... 60c/w dc electrical characteristics (4) t a = ? 40c to +85c, unless noted. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.5 3.3 2.625 3.6 v v i cc power supply current no loa d, max. v cc 20 30 ma r diff_in differential input resistance (in -to - /in) 90 100 110 ? r in input resistance (in -to -v t ), (/in -to -v t ) 45 50 55 ? v ih input high voltage (in, /in) note 5 v cc ? 1. 6 v cc v v il input low voltage (in, /in) 0 v ih ? 0.1 v v in in put voltage swing (in, /in) see figure 1a. 0.1 1.7 v v diff_in differential input voltage swing |in ? /in| see figure 1b. 0.2 v v t_in in -to -v t (in, /in) 1.28 v v ref ? ac output reference voltage v cc ? 1.3 v cc ? 1.2 v cc ? 1.1 v notes: 1. permanent device da mage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maxi mum rating condit ions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most n egative potential on the pcb. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been established . 5. v ih (min) not lower than 1.2v.
micrel, inc. sy89850u august 2 007 4 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 lvpecl output dc electrical characteristics (6) v cc = +2.5v 5% or +3.3v 10%; t a = ? 40c to +85c; r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ max units v cc output high voltage q, /q v cc ? 1.145 v cc ? 0.895 v v ol output low voltage q, /q v cc ? 1.945 v cc ? 1.695 v v out output voltage swing q, /q see figure 1a. 550 800 mv v diff_out differential output voltage swing q, /q see figure 1b. 1100 1600 mv note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establis hed. ac electrical characteristics (7) v cc = +2.5v 5% or +3.3v 10%; t a = ? 40c to +85c; r l = 50 ? to v cc ? 2v, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency nrz data 3.2 gbps v out 400mv clock 4 ghz t pd propagation delay in -to -q v in 100mv 180 260 360 ps t pd tempco differential propagation delay temperature coefficient 115 fs/c t jitter data random jitter (rj) deterministic jitter (dj) note 8 1 ps rms note 9 10 p s pp clock cycle -to - cycle jitter total jitte r (tj) note 10 1 ps rms note 11 10 p s pp t r , t f rise/fall time (20% to 80%) q, /q at full output swing. 50 100 160 ps notes: 7. the circuit is designed to meet the ac specifications shown in the above table after thermal equilibrium has been esta blished. 8. random jitter is measured with a k28.7 comma detect character pattern, measured at 2.5gbps and 3.2gbps. 9. deterministic jitter is measured at 2.5gbps and 3.2gbps, with both k28.5 and 2 23 ? 1 prbs pattern. 10. cycle - to - cycle jitter definition: th e variation of periods between adjacent cycles, t n ? t n -1 where t is the time between rising edges of the output signal. 11. total jitter definition: with an ideal clock input of frequency < f max , no more than one output edge in 10 12 output edges will devi ate by more than the specified peak - to - peak jitter value.
micrel, inc. sy89850u august 2 007 5 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 single- ended and differential swings figure 1a. singled - ended voltage swing figure 1b. differential voltage swing timing diagram
micrel, inc. sy89850u august 2 007 6 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 typical operating characteristics v cc = 3.3v, gnd = 0v, v in = 400mv pp , t r /t f 300ps, t a = 25c, unless otherwise stated.
micrel, inc. sy89850u august 2 007 7 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 functional characteristics v cc = 3.3v, gnd = 0v, v in = 400mv pp , t r /t f 300ps, t a = 25c, unless otherwise stated.
micrel, inc. sy89850u august 2 007 8 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 input and output stages figure 2a. simp lified differential input stage figure 2b. simplified lvpecl output stage input interface applications figure 3a. lvpecl interface (dc - coupled) figure 3b. lvpecl interface (ac - coupled) option: may connect v t to v cc figure 3c. cml interface (dc - coupled) figure 3d. cml interface (ac - coupled) figure 3e. lvds interface (dc - coupled)
micrel, inc. sy89850u august 2 007 9 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 output interface applications lvpecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. lvpecl is ideal for driving 50 ? - and 100 ? - controlled impedance transmission lines. there are several techniques for terminating the lvpecl output: parallel termination - thevenin equivalent, parallel termination (3 - resistor), and ac - co upled termination. unused output pairs may be left floating. however, single - ended outputs must be terminated, or balanced. note: 1. for +2.5v systems, r1 = 250 ?, r2 = 62.5?. figure 4a. parallel termination - thevenin equivalent notes: 1. power - savin g alternative to thevenin termination. 2. place termination resistors as close to destination inputs as possible. 3. r b resistor sets the dc bias voltage, equal to v t . 4. for 2.5v systems, r b = 19 ?. figure 4b. parallel termination (3 - resistor) related pro duct and support documentation part number function data sheet link sy58601u ultra - precision differential 800mv lvpecl line driver/receiver with internal termination www.micrel.com/product - info/products/sy58601u.shtml hbw solutions new products and appl ications www.micrel.com/product - info/products/solutions.shtml
micrel, inc. sy89850u august 2 007 10 m9999 - 083007-b hbwhelp@mic rel.com or (408) 955 - 1690 package information 8 - pin ultra - small epad dfn micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed by micr el for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or syste ms that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to res ult in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2005 micrel, incorporated.
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